DIFFERENCES BETWEEN RTL AND ARCHITECTURAL SYNTHESIS
Flash	Architectural synthesis	RTL synthesis
Design functionality	Manual by designer	Manual by designer
I/O behavior	Manual by designer	Manual by designer
Register insertion	Automatic, timing-driven	Manual, "logical" locations
Micro-architecture creation (throughput, latency, RAM interface, serial or parallel architecture, etc.)	Automatic, designer-guided	Manual by designer
Performance estimation	Automatic, technology-specific	"Guesstimation"
FSM generation	Automatically implemented	Manual by designer
Resource (adders, memory ports, etc.) selection	Automatic	Manual by designer