COMPARING DIE-PRODUCT PACKAGES
Package	Advantage	Disadvantage
ACF Flip-Chip (Anisotropically Conductive Film Adhesive Flip-Chip)	* Enables rapid prototyping * High connection density * Works where solder doesn't (e.g., on glass)	* Nonstandard pinout * Difficult to rework * Capitalization issues * Testing is difficult * Does not integrate into a standard surface-mount line
BGA (Ball Grid Array)	* High performance * Standard package * Easy to handle	* Very high cost per pin * Large compared to die
COB (Chip-On-Board)	* Lots of history * Ultralow cost * Standard wirebond die (no post-processing required) * Popular in Asia-Pacific (outside Japan)	* Higher parasitics than flip-chip * Peripheral leaded devices only * Does not integrate into standard surface-mount line
Flip-Chip	* Highest performance * Smallest outline * Low cost per pin * Self aligning (solder)	* Nonstandard pinout * Difficult to rework * Bumping costs * Testing is difficult
SIP (System-In-A-Package)	* High performance * Dense packaging * High integration	* Nonstandard package * High cost per pin * Testing is difficult
SP (Stacked Package)	* Very dense packaging (> 1.0 silicon to package ratio) * Standard package * Easy to handle	* Difficult to process very thin wafers * Unique designs costly
WL-CSP (Wafer-Level Chip-Scale Package)	* High performance * Dense package	* Nonstandard package * High cost per pin * Testing is difficult